View ST72682R20_4126420.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ST72682
USB 2.0 high-speed Flash drive controller
Features
USB 2.0 interface compatible with mass storage device class - Integrated USB 2.0 PHY - Supports USB high speed and full speed - Suspend and Resume operations Mass storage controller interface (MSCI) - Supports all types of NAND Flash devices including ST, Hynix, Samsung, Toshiba, Renesas, and Micron - Reed-Solomon encoder/decoder: on-thefly correction (4 bytes of a 512-byte block) - Flash identification support - Up to 21 Mbyte/s for read and 11 Mbyte/s for write operations in dual channel Embedded ST7 8-bit MCU Supply management - 3.3V operation - Integrated 3.3 -1.8 V voltage regulator USB 2.0 low-power device compliant - Less than 100 mA during write operation with two NAND Flash devices - Less than 500 A in suspend mode Clock management - Integrated PLL for generating core and USB 2.0 clock sources using external 12 MHz crystal Device summary

LQFP64 10x10
AutoRun CDROM partition support Data protection - Write protect switch control - Public/Private partitions support Bootability support (HDD mode) Production tool device configurability: - USB vendor ID/product ID (VID/PID), serial number and USB strings with foreign language support - SCSI strings - One or two LED outputs - Adjustable NAND Flash bus frequency to reach highest performance Code update in the NAND Flash LQFP64 10x10 lead-free package Development support - Complete reference design including schematics, BOM and gerber files Supports Windows (Vista, XP, 2000, ME), Linux and MacOS. Drivers available for Windows 98 SE
Orderable part numbers

Table 1.
Features ST72682/R20 USB interface Number of NAND devices supported Read/write speed Operating supply Operating Temperature Package USB 2.0 high speed up to 8 21MBps/11MBps 3.0 to 3.6 V 0C to +70C LQFP64 10x10 / die form ST72682/R21
August 2007
Rev 2
1/36
www.st.com 1
Contents
ST72682
Contents
1 2 3 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 NAND Flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 NAND Flash error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1.1 4.1.2 Hardware error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Firmware error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.1 4.2.2 4.2.3 Bad Block identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bad block replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Late Fail block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 4.4
Wear levelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 NAND Flash interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
Mass storage implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 5.2 USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 BOT/SCSI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.1 5.2.2 5.2.3 BOT specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SCSI specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bootability specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3
Multi-LUN device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.1 5.3.2 5.3.3 5.3.4 Public drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Private drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Additional drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CD-ROM considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4
Mass storage interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6
Human interface implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 6.2 LED behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read-only switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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ST72682
Contents
7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2 7.3 7.4 7.5 7.6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.5.1 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.6.1 7.6.2 7.6.3 Functional EMS (Electromagnetic Susceptibility) . . . . . . . . . . . . . . . . . 23 Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . 24
7.7
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.7.1 7.7.2 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.8 7.9
Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.8.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Other communication interface characteristics . . . . . . . . . . . . . . . . . . . . 30
7.9.1 7.9.2 MSCI parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 USB (Universal Bus Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8 9 10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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List of tables
ST72682
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Power supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Control and system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 USB 2.0 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 USB 2.0 and core clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General Purpose I/O ports / Mass Storage I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Known NAND Flash memory compatibility guide for ST72682/R20 and ST72682/R21. . . 12 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 RUN and SUSPEND modes current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Supply and Clock managers current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Typical CL and RS values by crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MSCI parallel interface DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 USB Interface DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 USB Interface AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 USB high speed transmit waveform requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 64-pin Thin Quad Flat Package (10 x10) mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . 33 Feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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ST72682
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 64-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Clock frequency versus supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Typical application with a crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Typical VIL and VIH standard I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Typical RPU vs. VDD33 with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Typical VOL at VDD33=3.3 V (I/O D2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Typical VOL at VDD33=3.3 V (I/O D4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Typical VOL at VDD33=3.3 V (I/O D8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Typical VDD33-VOH vs. VDD33 (I/O D2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Typical VDD33-VOH vs. VDD33 (I/O D4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Typical VDD33-VOH vs. VDD33 (I/O D8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Typical RON on RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Timing diagrams for input mode (with max load on CTRL signal = 50 pf) . . . . . . . . . . . . . 30 Timing diagrams for output mode (with max CTRL signal = 50 pf, DATA) . . . . . . . . . . . . . 30 USB signal eye diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 64-pin Thin Quad Flat Package (10 x10) package outline . . . . . . . . . . . . . . . . . . . . . . . . . 33
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Introduction
ST72682
1
Introduction
The ST72682 is a USB 2.0 high-speed Flash drive controller. The USB 2.0 high-speed interface includes PHY and function and supports USB 2.0 mass storage device class. The Mass storage controller interface (MSCI), combined with the Reed-Solomon encoder/decoder on-the-fly correction (4 bytes on 512-byte data blocks), provides a flexible high transfer rate solution for interfacing a wide of range NAND Flash memory devices. The internal 60 MHz PLL driven by the 12 MHz oscillator is used to generate the 480 MHz frequency required for the USB 2.0 PHY. The ST7 8-bit CPU runs the application program from the internal ROM and RAM. USB data and patch code are stored in internal RAM. The I/O ports provide allow to connect EEPROM, LEDs and a write protect switch control. The internal 3.3 to 1.8 V voltage regulator provides the 1.8 V supply voltage to the digital part of the circuit. Figure 1. Device block diagram
12 MHz OSC
8-bit CPU
ROM
RAM
USB 2.0 USB 2.0 Function PHY
Mass ReedStorage Solomon Controller Error Interface Correction
NAND I/F
3.3 V to 1.8 V voltage regulator
GPIO
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ST72682
Pin description
2
Pin description
Figure 2 shows the LQPF64 package pinout, while Table 2, Table 3, Table 4, Table 5, and Table 6 give the pin description. The legend and abbreviations used in these tables are the following:
Type - - - I = input O = output S = supply

Input level: A = Dedicated analog input In/Output level - - CT = CMOS 0.3VDD/0.7VDD with input trigger TT= TTL 0.8V / 2V with Schmitt trigger D8 = 8mA drive D4 = 4mA drive D2 = 2mA drive 64-pin LQFP package pinout
Output level - - -
Figure 2.
NAND D[13] NAND D[12] NAND D[11] NAND D[10] VDDA OSCIN OSCOUT VSSA RREF VSSC VDDC VDD3 USBDP USBDM VSSBL VDDBL
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS_1 VDD33_1 NC* NAND D[14] NAND D[15] NAND D[0] NAND D[1] NAND D[2] NAND D[3] NAND D[4] VSS_5 VDD33_5 NAND D[5] NAND D[6] NAND D[7] NAND RnB
ST72682
NAND WP READ ONLY NC(1) VSS_2 VDD33_2 NC(1) NC(1) RESET NC(1) NC(1) NC(1) LED2 LED1 PE4 NAND ALE VSS_3
1. Must remain NOT connected in the application.
VDDOUSB VSS_4 VDD33_4 NAND D[9] NAND D[8] NAND CE4 NAND CE3 NAND CE2 NAND CE1 NAND RE NAND WE NAND CLE NC(1) NC(1) NC(1) VDD33_3
7/36
Pin description Table 2.
Pin Pin name LQFP64 64 63 45 44 33 32 18 19 54 53 17 VSS_1 VDD33_1 VSS_2 VDD33_2 VSS_3 VDD33_3 VSS_4 VDD33_4 VSS_5 VDD33_5 VDDOUSB
ST72682 Power supply pins
Type Description
S Ground S I/Os and regulator supply voltage S Ground S I/Os and regulator supply voltage S Ground S I/Os and regulator supply voltage S Ground S I/Os and regulator supply voltage S Ground S I/Os and regulator supply voltage O USB2 PHY, OSC and PLL power supply output (1.8V)
Table 3.
Pin
Control and system
Level Power Type Input Pin name Output Description
LQFP64 41 RESET
I/O 3.3 CT
Reset input with filter with internal pull-up
Table 4.
Pin
USB 2.0 Interface
Type Pin name Description Supply voltage for buffers and deserialisation flip flops (1.8 V) Ground for buffers and deserialisation flip flops (1.8 V)
LQFP64 16 15 14 13 12 11 10 9 VDDBL VSSBL USBDM USBDP VDD3 VDDC VSSC RREF
S S
I/O USB2 DATA I/O USB2 DATA + S S S I/O Supply voltage for the FS compliance (3.3 V) Supply voltage for DLL & XOR tree (1.8 V) Ground for DLL & XOR tree (1.8 V) Ref. resistor for integrated impedance process adaptation (11.3 kOhms 1% Pull Down)
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ST72682 Table 5.
Pin Pin name LQFP64 8 7 6 5 VSSA OSCOUT OSCIN VDDA
Pin description USB 2.0 and core clock system
Type Description
S Ground for oscillator & PLL (1.8 V) O 12MHz oscillator output I 12MHz oscillator input
S Supply voltage for oscillator & PLL (1.8 V)
Table 6.
Pin
General Purpose I/O ports / Mass Storage I/Os
Level Input Pin name Outputs Main function (after reset) Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O
LQFP64 59 58 57 56 55 52 51 50 21 20 10 11 12 13 14 15 34 35 28 27 26 25 24 23 NAND D[0] NAND D[1] NAND D[2] NAND D[3] NAND D[4] NAND D[5] NAND D[6] NAND D[7] NAND D[8] NAND D[9] NAND D[10] NAND D[11] NAND D[12] NAND D[13] NAND D[14] NAND D[14] NAND ALE PE4 NAND CLE NAND WE NAND RE NAND CE1 NAND CE2 NAND CE3
TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT TT
D4 NAND data [0] D4 NAND data [1] D4 NAND data [2] D4 NAND data [3] D4 NAND data [4] D4 NAND data [5] D4 NAND data [6] D4 NAND data [7] D4 NAND data [8] D4 NAND data [9] D4 NAND data [10] D4 NAND data [11] D4 NAND data [12] D4 NAND data [13] D4 NAND data [14] D4 NAND data [15] D8 NAND address latch enable D2 D8 NAND command latch enable D8 NAND write enable D8 NAND read enable D4 NAND enable 1 D4 NAND enable 2 D4 NAND enable 3
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Pin description Table 6.
Pin Type Pin name LQFP64 22 49 48 47 NAND CE4 NAND RnB NAND WP READ ONLY EEPROM SCL 37 36 LED2 LED1
ST72682 General Purpose I/O ports / Mass Storage I/Os (continued)
Level Outputs Input Main function (after reset)
O I O I O O O
TT TT TT TT TT TT TT
D4 NAND enable 4 D2 NAND Ready/Busy D2 NAND Write Protect D2 Read-only switch ("0": Read/Write; "1": Read only) D2 EEPROM serial clock D8 Green LED (USB access) D8 Red LED (NAND access)
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3
ST72682
Figure 3.
U1b
AME8800_SOT23
3 Vin
GND
Vout V33
U2
2
On Board Flash1
NAND_RnB
D[7..0]
1
V33
NAND_WP R3 4.7K NAND_WP U1a
USB_V5 1 Vin GND INHI BI T BYPASS
LD3985M33R_SOT235L C1 10nF
Vout
5
2 3
NAND_RnB
C4
C10
4 V33
R_SW 0 R_Samsung W_config GND/NAND_RnB2 NAND_WP NAND_CE3 NAND_CE4 NAND _CL E NAND_AL E NAND_WE NAND_WP
1uF
100nF
+ C6 4.7uF C7 220nF C8 100nF C9 100nF C2 10nF
NAND_RnB NAND_RnB GND/NAND_RnB2 NAND_RnB NAND_RE NAND_CE1 NAND_CE2 D7 D6 D5 D4
Application schematic
V33
D3 D2 D1 D0
V33
D[7..0] R_T 0 R_Toshiba_config R4 10K
D[15..8]
V33
D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 NAND_RnB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NC/#RES NC NC NC NC NC NC/#RB4 NC NC/#RB3 I/O 7 GND/#RB2/NC I/O 6 #RB/#RB1 I/O 5 #RE I/O 4 #CE/#CE1 NC NC/#CE2 NC NC NC/PRE VCC VCC VSS VSS NC/#CE3 NC NC/#CE4 NC CL E NC AL E I/O 3 #WE I/O 2 #WP I/O 1 NC I/O 0 NC NC NC NC NC NC NC NC
NAND_FLASH_TSOP 48
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
Application schematics
V18_USB
U4 RO Read Only NAND_WP NAND_WP
V18_USB
S1
XT1
4 V33 V33
2
V18_USB
On Board Flash2
U3 NAND_WP NAND_RnB
12MHz_NX4025DA
D13 D12 D11 D10 LED1 RED L ED LED2 GREEN ED L
R6 RESET ST72682_QF64 P
VSS_1 VDD33_1 NC NAND D[14] NAND D[15] NAND D[0] NAND D[1] NAND D[2] NAND D[3] NAND D[4] VSS_5 VDD33_5 NAND D[5] NAND D[6] NAND D[7] NAND RnB
510
NAND_RnB NAND_RnB GND/NAND_RnB2 NAND_RnB NAND_RE NAND_CE1 NAND_CE2
D15 D14 D13 D12
J1 LED2 LED1 NAND_AL E
LED1
V33
R1 330
LED2
V33
R2 330
GND D+ DVBUS
4 3 2 1
DP DM
V33
USB_V5
C11 100nF
1 2 3 4 5 OSCIN 6 OCSOUT 7 8 9 RREF 10 11 12 13 14 15 16 NAND D[13] NAND D[12] NAND D[11] NAND D[10] VDDA OSCI N OSCOUT VSSA RREF VSSC VDDC VDD3 USBDP USBDM VSSBL VDDBL NAND WP READ ONL Y NC VSS_2 VDD33_2 NC NC RESET NC NC NC LED2 LED1 NC NAND AL E VSS_3
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
USB CON
NAND_CE3 NAND_CE4 NAND _CL E NAND_AL E NAND_WE NAND_WP
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDDOUSB VSS_4 VDD33_4 NAND D[9] NAND D[8] NAND CE4 NAND CE3 NAND CE2 NAND CE1 NAND RE NAND WE NAND CLE NC NC NC VDD33_3
R5 11.3K 1%
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
NC/#RES NC NC NC NC NC NC/#RB4 NC NC/#RB3 I/O 7 GND/#RB2/NC I/O 6 #RB/#RB1 I/O 5 #RE I/O 4 #CE/#CE1 NC NC/#CE2 NC NC NC/PRE VCC VCC VSS VSS NC/#CE3 NC NC/#CE4 NC CL E NC AL E I/O 3 #WE I/O 2 #WP I/O 1 NC I/O 0 NC NC NC NC NC NC NC NC
NAND_FLASH_TSOP 48
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
D11 D10 D9 D8
V33
D9 D8
NAND_CE4 NAND_CE3 NAND_CE2 NAND_CE1 NAND_RE NAND_WE NAND_CLE
C3 10nF
C5 470nF
V33
D[15..8]
C12 18pF
3
1
C13 18pF
Application schematics
11/36
NAND Flash memory interface
ST72682
4
NAND Flash memory interface
Table 7 gives the list of NAND Flash memory devices compatible with ST72682/R20 and ST72682/R21 devices. This list is only provided as a guide as it is not possible to automatically guarantee support for all the additions and updates across the listed ranges of manufacturers' devices.
Table 7.
Known NAND Flash memory compatibility guide for ST72682/R20 and ST72682/R21
NAND Flash size (Mbytes or Gbytes) and type 128 MB; SLC2K; Single CE 256 MB; SLC2K; Single CE 512 MB; SLC2K; Single CE 512 MB; SLC2K; Single CE 512 MB; SLC2K; Dual CE 1 GB; SLC2K; Single CE 1 GB; SLC2K; Dual CE 2 GB; SLC2K; Dual CE 4 GB; SLC2K; Quad CE 512 MB; MLC2K; Single CE 1 GB; MLC2K; Single CE 2 GB; MLC2K; Dual CE 4 GB; MLC2K; Quad CE 128 MB; SLC2K; Single CE 256 MB; SLC2K; Single CE 512 MB; SLC2K; Single CE 256 MB; MLC2K; Single CE 512 MB; MLC2K; Single CE 1 GB; MLC2K; Single CE 128 MB; SLC2K; Single CE 256 MB; SLC2K; Single CE 512 MB; SLC2K; Single CE 1 GB; SLC2K; Single CE 512 MB; MLC2K; Single CE 128 MB; SLC2K; Single CE 256 MB; SLC2K; Single CE 512 MB; SLC2K; Single CE 512 MB; SLC2K; Dual CE Number of NAND Flash devices supported ST72682/R20 device 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 2 or 4 1, 2, 4, 6 or 8 2 or 4 2 or 4 2 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 2 or 4 2 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 2 or 4 ST72682/R21 device 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2 or 4 1, 2, 4, 6 or 8 1, 2 or 4 1, 2 or 4 1 or 2 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2 or 4 1 or 2 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2 or 4
NAND Flash part number Samsung K9F1G08U Samsung K9F2G08U Samsung K9F4G08U Samsung K9K4G08U Samsung K9W4G08U Samsung K9K8G08U Samsung K9W8G08U Samsung K9WAG08U Samsung K9NBG08U Samsung K9G4G08U Samsung K9L8G08U Samsung K9HAG08U Samsung K9MBG08U Toshiba TH58NVG0S3 Toshiba TH58NVG1S3 Toshiba TH58NVG2S3 Toshiba TH58NVG1D4 Toshiba TH58NVG2D4 Toshiba TH58NVG3D4 ST NAND01GW3B ST NAND02GW3B ST NAND04GW3B ST NAND08GW3B ST NAND04GW3C Hynix HY27UF081G2M Hynix HY27UG082G2M Hynix HY27UG084G2M Hynix HY27UH084G5M
12/36
ST72682 Table 7.
NAND Flash memory interface Known NAND Flash memory compatibility guide for ST72682/R20 and ST72682/R21
NAND Flash size (Mbytes or Gbytes) and type 1 GB; SLC2K; Single CE 512 MB; MLC2K; Single CE 1 GB; MLC2K; Dual CE 256 MB; SLC2K; Single CE 512 MB; SLC2K; Single CE 1 GB; SLC2K; Dual CE Number of NAND Flash devices supported ST72682/R20 device 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 2 or 4 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 2 or 4 ST72682/R21 device 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2 or 4 1, 2, 4, 6 or 8 1, 2, 4, 6 or 8 1, 2 or 4
NAND Flash part number Hynix HY27UH088G2M Hynix HY27UT084G2M Hynix HY27UU088G5M Micron 29F2G08AA Micron 29F4G08BA Micron 29F8G08FA
4.1
NAND Flash error correction
No NAND Flash memory arrays are guaranteed by manufacturers to be error-free. Error occurrence depends on the Flash cell type (MLC or SLC). The ST72682 embeds hardware and firmware mechanisms to correct the errors.
4.1.1
Hardware error correction
The ST72682 embeds a Reed-Solomon algorithm-based hardware cell. This cell directly manages 512-byte data packets on the NAND I/O system. Based on the data packet content, the cell generates an 80-bit Error Correction Code (ECC) consisting of 8 words, each containing 10 bits. During write operations to NAND memory, the 512-bytes of data and the ECC are stored together in the same page. The ECC is stored in the corresponding Redundant Area (RA), using 10 bytes. During read operations, the 512-bytes of data and the 8 ECC words are read back and are passed through the Reed-Solomon cell for decoding. The cell allows the correction of 4 symbols in this 520-symbol packet (512 symbols from data + 8 symbols from ECC). The hardware cell gives three possible results:

No error detected: the data packet can be used as it is. Correctable error detected: the corrected data are available in a specific 512-byte buffer in the Reed-Solomon cell and are ready to be used. Uncorrectable error detected: data corruption cannot be repaired.
4.1.2
Firmware error management
The firmware defines the error correction possibilities with the corrected data packet. When data cannot be repaired, the block is considered as a bad block and is replaced by another one. See Section 4.2 for further information on bad block management.
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NAND Flash memory interface
ST72682
4.2
Bad block management
NAND memory manufacturers deliver their devices with factory-marked bad blocks. This marking depends on the manufacturer and the NAND memory type (page size, memory technology, etc.). The ST72682 supports all bad block markings currently available on the market.
4.2.1
Bad Block identification
During firmware initialization, the MCU scans the entire NAND memory configuration to identify bad blocks. A bad block is defined as follows:

Five different block status bytes are considered: 4 status bytes from page 0 and 1 from an other page (page 127 for MLC NAND; page 1 for SLC NAND). The considered block is marked as a bad block if one out of these five bytes contains at least four bits set to `0'.
4.2.2
Bad block replacement
The firmware works on groups of 1024 blocks, called zones. A complete NAND configuration can contain several zones:

Each zone is described in a Look Up Table (LUT) containing 1024 entries. A LUT is composed of 3 parts: used blocks, free blocks and bad blocks. The "bad blocks" part contains as many entries as the number of bad blocks identified in that zone. The "used blocks" part can have a size of 1000, 900 or 500 entries. This size is configurable and also depends on the number of identified bad blocks. The "free blocks" part contains the remaining entries.
The used blocks part is used to do a correspondence between NAND blocks and logical address ranges. This system allows all bad blocks to be masked from the Host. As a result, bad blocks are never seen. Only a range of logical addresses are visible which correspond to the sum of the used blocks part of all zones.
4.2.3
Late Fail block
During normal application life, defects may appear in the NAND memory. Under certain conditions, these defects are not correctable and the corresponding block is declared as "bad". In this case, new bad blocks are identified in the bad blocks part of the LUT and replaced by new blocks from the "free blocks" part.
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ST72682
NAND Flash memory interface
4.3
Wear levelling
During normal application life, the NAND memory is written and erased (at block level) many times. The NAND device is guaranteed for a limited number of write operations (about 100 000 cycles). As a consequence, the controller must keep write/erase operations to a minimum for any individual block. A method to limit these cycles is to use a "Wear Levelling" scheme between all NAND memory blocks.
LUT usage
The LUT is used for transfers between a logical address range and a block. It contains free blocks which are used in the "wear levelling" scheme. During write command treatment, the firmware calculates the zones, blocks and pages for data write access. In a block write operation, the firmware applies the following scheme to avoid block wearing:

The least recently-used block is chosen from the free block part of the LUT. Valid data from the old block is copied to the new block. New data from the write command is written to the new block. The old block is erased. The LUT is updated after identifying the new block in the used block part and the old block in the free block part.
Using this scheme, a logical address range doesn't correspond to a constant block. A write command repeated several times to the same logical address writes physically into different blocks. This method shares the wearing evenly across all blocks of the concerned zone.
4.4
NAND Flash interface configuration
Applications based on ST72682 can be configured through a dedicated PC software tool. The NAND memory RE and WE signals frequencies can be independently configured to 30 MHz, 20 MHz, 15 MHz, 12 MHz and 10 MHz. The logical size reduction factor can be configured to 90% or 50% in the event of having too many bad blocks. this option resizes the used blocks part of the LUT to 900 or 500.
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Mass storage implementation
ST72682
5
5.1
Mass storage implementation
USB characteristics
The ST72682 is compliant with USB 2.0 specification. It is able to operate in both high speed and full speed modes using a bidirectional control endpoint 0 and a bidirectional bulk endpoint 2. It automatically recognizes the speed to use on the bus by a process of negotiation with USB Host.
5.2
5.2.1
BOT/SCSI implementation
BOT specification
The USB Mass Storage Class Bulk Only Transport (BOT) specification version 1.0 is implemented. It allows the device to be recognized by the host as a mass-storage USB device.
5.2.2
SCSI specification
Moreover, inside BOT transfers, SCSI commands are encapsulated for mass storage operations. The related specifications are SBC-2 revision 10 (SCSI Block Commands 2) and SPC-4 revision 7a (SCSI Primary Commands 4).
5.2.3
Bootability specification
The USB mass storage specification for bootability revision 1.0 is implemented. It allows the PC host to boot the operating system from the USB mass storage application. In this case, the Host uses BOT LUN 0 (logical unit number). A specific tool must be used to format the logical drive in order to make it bootable by programming the correct information.
5.3
Multi-LUN device characteristics
The application can be configured with a dedicated PC software tool as a multi-LUN device. In this case, up to 3 different drives are available: public drive, additional drive and private drive. Public and additional drives can be configured as removable drive, hard disk drive or CDROM drive.
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ST72682
Mass storage implementation
5.3.1
Public drive
The public drive is the default configuration in a mono-LUN mode. In this default case, it is declared as a removable drive. The public drive is mandatory and can not be removed from the configuration. By customization (using PC software), it can be declared as a removable drive, a CD-ROM drive or a hard disk drive. This drive is the LUN 0 in BOT commands.
5.3.2
Private drive
The Private drive is optional. Its type is "removable drive" and is not configurable. This drive is protected by password and cannot be directly accessed through the PC operating system. A PC software tool is necessary to send a command with the password to unlock the device. The device is then open and accessible by the PC operating system until reset or reception of a new command to lock the drive. This drive is the LUN 1 in BOT commands.
5.3.3
Additional drive
The additional drive is optional. Its type can be "removable drive", "hard disk drive" or "CDROM drive". This drive is LUN 1 in BOT commands if the private drive option is not active, and is LUN 2 if the private drive option is active.
5.3.4
CD-ROM considerations
When a drive is declared as CD-ROM, the ST72682/R21 manages this drive with a logical block size of 2 Kbytes. To be correctly recognized by the host, it is preferable to build a CDFS partition on this CD-ROM. See the `ST7268x Production Tool User Manual' for more information. Note that the ST72682/R20 doesn't consider the CD-ROM partition as a specific case. The logical block size is 512 bytes and any file system can be used. In both cases, the CD-ROM partition allows the use of the AutoRun operating system feature. During device connection, the CD-ROM partition is recognized and the host tries to run the application corresponding to the autorun.inf file present into this CD-ROM partition.
5.4
Mass storage interface configuration
In addition to the parameters already described as configurable in the previous chapters, additional customizable information includes:

USB parameters: VID, PID, all string information. SCSI parameters: strings for inquiry commands.
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Human interface implementation
ST72682
6
6.1
Human interface implementation
LED behavior
The application is designed to manage 2 LEDs. This behavior is configurable through PC dedicated software: `ST7268x Production Tool'. By default, LED 1 responds to NAND memory access activity and LED 2 responds to USB activity. Use of LED 1 is optional. When this option is not active, LED 2 reacts to both USB and NAND memory activity.
6.2
Read-only switch
The READ ONLY pin of the ST72682 is an input pin to be connected to VDD or GND depending on the behavior of the device.

When this pin is connected to GND, no limitations are applied on the PC command received. When this pin is connected to VDD or unconnected, the firmware filters all accesses to the NAND memory which modify the NAND memory state (write, erase, etc.) and returns an error to the PC.
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ST72682
Electrical characteristics
7
7.1
Electrical characteristics
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
7.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the Devices with an ambient temperature at TA=25 C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3).
7.1.2
Typical values
Unless otherwise specified, typical data are based on TA=25 C, VDD33=3.3 V. They are given only as design guidelines and are not tested.
7.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
7.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 4. Figure 4. Pin loading conditions
DEVICE PIN
CL
19/36
Electrical characteristics
ST72682
7.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 5. Figure 5. Pin input voltage
DEVICE PIN VIN
7.2
Absolute maximum ratings
Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the Device. This is a stress rating only and functional operation of the Device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 8. Voltage characteristics
Ratings Supply voltage Input voltage on any other pin Electrostatic discharge voltage (Human Body Model) Maximum value 4.0 VSS-0.3 to VDD33+0.3 Unit V V
Symbol VDD33 - VSS VIN(1)(2)
VESD(HBM)
see Section 7.6.3: Absolute Maximum Ratings (Electrical Sensitivity)
1. Directly connecting the RESET and I/O pins to VDD33 or VSS could damage the Device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k for RESET, 10k for I/Os). For the same reason, unused I/O pins must not be directly tied to VDD33 or VSS. 2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN) specification. A positive injection is induced by VIN>VDD33 while a negative injection is induced by VINTable 9.
Symbol IVDD33 IVSS
Current characteristics
Ratings Total current into VDD33 power lines (source)(1) Total current out of VSS ground lines (sink)(1) Maximum value 200 200 25 mA 35 50 -25 Unit
Output current sunk by any I/O D2 type IIO(2) Output current sunk by any I/O D4 type Output current sunk by any I/O D8 type Output current source by any I/Os and control pin
1. All power supply (VDD33) and ground (VSS) lines must always be connected to the external supply. 2. Refer to Table 6 for the output drive capability of each of the I/Os.
20/36
ST72682 Table 10. Thermal characteristics
Ratings Storage temperature range Maximum junction temperature
Electrical characteristics
Symbol TSTG TJMAX
Value -65 to +150 120
Unit C C
7.3
Operating conditions
Table 11.
Symbol VDD33 TA
General operating conditions
Parameter Power Supply Ambient temperature range Conditions Min 3.0 0 Max 3.6 70 Unit V C
Figure 6.
Clock frequency versus supply voltage
fCPU [MHz] FUNCTIONALITY GUARANTEED IN THIS AREA
30
FUNCTIONALITY T GUARANTEED 15 IN THIS AREA
6 3 0 2.0 2.5 2.7 3.0 3.3 3.6
SUPPLY VOLTAGE [VDD33]
7.4
Supply current characteristics
Table 12.
Symbol IDD
RUN and SUSPEND modes current
Parameter Supply current in RUN mode Supply current in SUSPEND mode Conditions fOSC=12MHz VDD33=3.3V, TA=+25C Min 15 60 Typ 25 90 Max 35 190 Unit mA A
Table 13.
Symbol IDD(CK)
Supply and Clock managers current
Parameter Supply current of crystal oscillator(3) Conditions Typ(1) Max(2) 1000 2000 Unit A
1. Typical data are based on TA=25 C and fCPU=12 MHz. 2. Data based on characterization results, not tested in production. 3. Data based on characterization results done with the external components specified in Section 7.5.1, not tested in production.
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Electrical characteristics
ST72682
7.5
Clock and timing characteristics
Subject to general operating conditions for VDD33, fOSC, and TA.
7.5.1
Crystal oscillator
The Device internal clock is supplied from a crystal oscillator. All the information given in this paragraph are based on characterization results with specified typical external components. In the application the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal manufacturer for more details (frequency, package, accuracy...). Table 14.
Symbol fOSC CKACC OSC
Clock characteristics
Parameter Oscillator frequency Total crystal oscillator accuracy Crystal oscillator duty cycle(1) Absolute value + temperature + aging 45 50 Conditions Min Typ 12 60 55 Max Unit MHz ppm %
1. The crystal oscillator duty cycle has to be adjusted through the two CL capacitors. Refer to the crystal manufacturer for more details.
Figure 7.
Typical application with a crystal
VDDA
CL OSCIN CRYSTAL CL RSOSCOUT
(1)
OSCOUT
Device
1. Depending on the crystal power dissipation, a serial resistor RsOscout may be added. Refer to the crystal manufacturer for more details.
Table 15.
Typical CL and RS values by crystal
Supplier NDK Typical Crystal AT51 or AT41 CL (pF) 16 RSOSCOUT () 560
22/36
ST72682
Electrical characteristics
7.6
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
7.6.1
Functional EMS (Electromagnetic Susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
ESD: Electrostatic Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD33 and VSS33 through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.
Software recommendations The software flowchart must include the management of runaway conditions such as: - - - Corrupted program counter Unexpected reset Critical Data corruption (control registers...)
Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Table 16.
Symbol VFESD
EMS characteristics
Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance Fast transient voltage burst limits to be applied through 100pF on VDD33 and VSS33 pins to induce a functional disturbance Conditions VDD33=3.3 V, TA=+25 C, fOSC=12 MHz compliant with IEC 1000-4-2 Level/Class 4B
VFFTB
VDD33=3.3 V, TA=+25 C, fOSC=12 MHz compliant with IEC 1000-4-4
4A
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Electrical characteristics
ST72682
7.6.2
Electromagnetic Interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. Table 17. EMI characteristics
Conditions Monitored Frequency Band 0.1 to 30 MHz VDD33=3.3 V, TA=+25 C, conforming to SAE J 1752/3(1) 30 to 130 MHz 130 MHz to 1 GHz SAE EMI Level
1. Refer to Application Note AN1709 for data on other package types.
Symbol Parameter
Max vs. (fOSC at 12 MHz) 20 25 25 4
Unit
dBV
SEMI
Peak level
-
7.6.3
Absolute Maximum Ratings (Electrical Sensitivity)
Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.
Electrostatic Discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. Table 18.
Symbol VESD(HBM)
Absolute maximum ratings
Ratings Electrostatic discharge voltage (Human Body Model) Conditions TA=+25C Maximum value(1) 2000 Unit V
1. Data based on characterization results, not tested in production.
Static and Dynamic Latch-Up
LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. DLU: Electrostatic discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181.
24/36
ST72682 Table 19.
Symbol LU DLU
Electrical characteristics Electrical sensitivities
Parameter Static latch-up class Dynamic latch-up class Conditions TA=+25 C VDD33=3.3 V, fOSC=12 MHz, TA=+25 C Class(1) A A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard).
7.7
7.7.1
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD33, fOSC, and TA unless otherwise specified.
Table 20.
Symbol VIL VIH Vhys IL RPU
I/O port characteristics
Parameter Input low level voltage(1) Input high level voltage(1) TTL ports 0.85VDD33 400 VSS VIN VDD33, standard I/Os VIN=VSS VDD33= 3.3 V 32 50 1 75 mV A k Conditions Min Typ Max 0.16VDD33 Unit V
Schmitt trigger voltage hysteresis(2) Input leakage current Weak pull-up equivalent resistor(1)
1. The RPU pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results, tested in production at VDD33 max. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.
Figure 8.
Two typical applications with unused I/O pin
VDD33 10k UNUSED I/O PORT Device
UNUSED I/O PORT 10k Device
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Electrical characteristics
ST72682
Figure 9.
Typical VIL and VIH standard I/Os
V IL/ V IH ( V ) 2.5
Figure 10. Typical RPU vs. VDD33 with VIN=VSS
I/ O s pull- up re s is t a nc e
2 1 .5 1 0.5 0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VD D (V)
I/Os pull-up resistance (kW)
60 50 40 30 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VD D (V)
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VIL/VIH (V)
ST72682
Electrical characteristics
7.7.2
Output driving current
Subject to general operating conditions for VDD33, fOSC, and TA unless otherwise specified. Table 21.
Symbol
Output driving current
Parameter Output low level voltage for a D2 I/O pin when 8 pins are sunk at same time (see Figure ) Conditions IIO=2mA Min Max 300 Unit
VOL(1)
Output low level voltage for a D4 I/O pin when 8 pins are sunk at same time (see Figure 12)
VDD33=3.3 V
IIO=4mA
400
mV
Output low level voltage for a D8 I/O pin when 8 pins are sunk at same time (see Figure 13) Output high level voltage for a D2 I/O pin when 8 pins are sourced at same time (see and Figure 14) VDD33VOH(2) Output high level voltage for a D4 I/O pin when 8 pins are sourced at same time (see Figure 15) Output high level voltage for a D8 I/O pin when 8 pins are sourced at same time (see Figure 16)
IIO=8mA
500
IIO=2mA
600
IIO=4mA
600
mV
IIO=8mA
600
1. The IIO current sunk must always respect the absolute maximum rating specified in Section Table 9. and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section Table 9. and the sum of IIO (I/O ports and control pins) must not exceed IVDD33. True open drain I/O pins does not have VOH.
Figure 11. Typical VOL at VDD33=3.3 V (I/O D2)
V O L I/ O s D 2 a t V D D =3 .3 V
Figure 12. Typical VOL at VDD33=3.3 V (I/O D4)
V O L I/ O s D 4 a t V D D =3 .3 V
VOL 2mA (mV)
1 50 1 00 50 0 0 1 2 IO L ( m A ) 3 4
VOL 4mA (mV)
1 50 1 00 50 0 0 2 IO L ( m A ) 4 6
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Electrical characteristics
ST72682
Figure 13. Typical VOL at VDD33=3.3 V (I/O D8)
V O L I/ O s D 8 a t V D D =3 .3 V
Figure 14. Typical VDD33-VOH vs. VDD33 (I/O D2)
V D D - V O H I/ O s D 2 a t V D D =3 .3 V
VOL 8mA (mV)
1 50 1 00 50 0 0 5 IO L ( m A ) 1 0
VOH 2mA (mV)
200 1 50 1 00 50 0 0 2 IO H ( m A ) 4
Figure 15. Typical VDD33-VOH vs. VDD33 (I/O D4) Figure 16. Typical VDD33-VOH vs. VDD33 (I/O D8)
V D D - V O H I/ O s D 4 a t V D D =3 .3 V
V D D - V O H I/ O s D 8 a t V D D =3 .3 V
VOH 4mA (mV)
VOH 8mA (mV)
1 50 1 00 50 0 0 2 IO H ( m A ) 4 6
200 1 50 1 00 50 0 0 5 IO H ( m A ) 1 0
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ST72682
Electrical characteristics
7.8
7.8.1
Control pin characteristics
Asynchronous RESET pin
TA ranges between 0 and +55 C unless otherwise specified. Table 22.
Symbol VIL VIH Vhys RON
.
Asynchronous RESET pin characteristics
Parameter Input low level voltage(1) Input high level voltage Schmitt trigger voltage hysteresis(1) Pull-up equivalent resistor VDD33 = 3.3 V VDD33 = 2 V 2.5 200 500 2 duration(3) 20 0.85VDD33 450 40 100 s ns s Tcpu 80 k mV Conditions Min Typ Max 0.16VDD33 Unit V
teh(RSTL) External reset pulse hold time(2) tg(RSTL) Filtered glitch tew(RSTL) External reset pulse duration(4) tiw(RSTL) Internal reset pulse duration
1. The level on the RESET pin must be free to go below the VIL max. level specified in Section 7.8.1. Otherwise the reset will not be taken into account internally. 2. To guarantee the reset of the Device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below teh(RSTL) can be ignored. Not tested in production, guaranteed by design. 3. The reset network protects the device against parasitic resets. 4. The external reset duration must respect this timing to guarantee a correct start-up of the internal regulator at power-up. Not tested in production, guaranteed by design.
Figure 17. Typical RON on RESET pin
NRESET pull-up (kOhms) NRESET pull-up (kOhms) 100 80 60 40 2 3 VDD (V)
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Electrical characteristics
ST72682
7.9
7.9.1
Other communication interface characteristics
MSCI parallel interface
Figure 18. Timing diagrams for input mode (with max load on CTRL signal = 50 pf)
CTRL
external
DATA
ext device
DATA(i)
DATA(i+1)
tDS(1) 1. tDS is the setup time for data sampling.
Figure 19. Timing diagrams for output mode (with max CTRL signal = 50 pf, DATA)
CTRL
external
DATA
external
DATA(i)
DATA(i+1)
tDO(1)
1. tDO is the data output time for data sampling.
Table 23.
MSCI parallel interface DC characteristics
MSCI DC Electrical Characteristics
Parameter Data setup time Data output time CTRL line capacitance Data line capacitance
Symbol tDS tDO Cctrl Cdata
Conditions
Min.
Typ(1) 11 6 50 50
Max.
Unit ns ns pF pF
1. Data based on design simulation and not tested in production.
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ST72682
Electrical characteristics
7.9.2
USB (Universal Bus Interface)
Table 24.
Symbol
USB Interface DC characteristics
Parameter Conditions VDD33=3.3 V, regulator and PHY ON Min. 0.5(1) 60 Typ. 1.5 90 1.5 Full Speed Mode Max. Unit 6(1) 190 mA A k
IDDsuspend Suspend current
VDD33=3.3 V, Powerdown mode, 25 C (2)
RPU
Pull-up resistor(1)
VTERM VOH VOL VCRS
Termination voltage High level output voltage Low level output voltage Crossover voltage High Speed Mode
0.8 2.8
2.0 3.6 0.8
V V V V
1.3
2.0
VHSOH VHSOL
HS data signalling high HS data signalling low
400 5
mV mV
1. Not tested in production, guaranteed by characterization. 2. In order to reach this value, the software must force the regulator into power-down mode and the I/Os compensation cell off.
Table 25.
Symbol
USB Interface AC timing
Parameter Conditions Full Speed Mode Min. Max. Unit
TFR TFF
Rise Time Fall Time
CL=50pF CL=50pF High Speed Mode
4 4
20 20
ns ns
THSR THSF THSDRAT
Rise Time Fall Time HS Data Rate 479.76
500(1) 500(1) 480.24
ps ps Mb/ s
1. Not tested in production, guaranteed by characterization.
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Electrical characteristics Figure 20. USB signal eye diagram
ST72682
Table 26.
USB high speed transmit waveform requirements
Voltage Level (DP - DN) Time 2.082 to 2.084 ns 5% UI 95% UI 35% UI 65% UI 35% UI 65% UI
Unit Interval (UI) Level 1 Level 2 Point 1 Point 2 Point 3 Point 4 Point 5 Point 6
475 mV -475 mV 0V 0V 300 mV 300 mV -300 mV -300 mV
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ST72682
Package mechanical data
8
Package mechanical data
Figure 21. 64-pin Thin Quad Flat Package (10 x10) package outline
D D1 A1 A A2
b E1 E e
L1 L
c
Table 27.
Dim.
64-pin Thin Quad Flat Package (10 x10) mechanical data
mm Min Typ Max 1.60 0.05 1.35 0.17 0.09 12.00 10.00 12.00 10.00 0.50 0 0.45 3.5 0.60 1.00 Number of pins 7 0.75 0 0.018 1.40 0.22 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.004 0.472 0.394 0.472 0.394 0.020 3.5 0.024 0.039 7 0.030 0.055 0.009 Min inches Typ Max 0.063 0.006 0.057 0.011 0.008
A A1 A2 b c D D1 E E1 e L L1
N
64
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Device ordering information
ST72682
9
Device ordering information
Table 28. Feature comparison
Description AutoRun runs a program when the USB Flash drive is inserted into a computer.
Features added in the ST72682/R21 versus ST72682/R20 Continued AutoRun CDROM partition support
Table 29.
Ordering Information
Package LQFP64 10x10mm LQFP64 10x10mm Operating voltage 3.0V to 3.6V 3.0V to 3.6V Temperature range 0C to +70 C 0C to +70 C
Orderable part number ST72682/R20 ST72682/R21 (latest firmware revision
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ST72682
Revision history
10
Revision history
Table 30.
Date 09-Feb-2006 14-Aug-2007
Document revision history
Revision 1.0 2.0 Initial release Firmware revision updated to R21. References to TQFP64 updated to LQFP64. Datasheet reformatted. Description of Changes
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ST72682
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